1. Field of the Invention
The present invention relates to a level conversion circuit connected to a logic circuit included in a radio-frequency signal switching device used in a communication terminal apparatus (a cellular telephone, wireless communication unit or the like).
2. Description of the Background Art
In recent years, there has been an increased demand that a radio-frequency signal switching device be of a multi-input multi-output type. The radio-frequency signal switching device of this type requires a logic circuit. The logic circuit outputs a signal to any of four output terminals corresponding, respectively, to four types of combinations (00, 01, 10, 11) of input signals, each having two bits, for example.
However, a voltage range as “Low” and a voltage range as “High”, both of which are allowable for the logic circuit does not necessarily coincide with a voltage range of a signal outputted from a circuit provided preceding to the logic circuit. For example, when a baseband circuit provided preceding to the logic circuit is a C-MOS output circuit, “Low” is 0V and “High” is 1.8V or more, while when the logic circuit is a gallium arsenide metal semiconductor field-effect transistor (GaAs-MESFET), “Low” is 0V and “High” is approximately 0.2V or more, for example. Under such circumstances, a level conversion circuit is necessary to be provided.
FIG. 13 is a diagram illustrating an example of a schematic structure of a radio-frequency signal switching device including a level conversion circuit. In an example shown in FIG. 13, a SW circuit 140 has one input and four outputs. A baseband circuit 110 outputs a control signal for which the SW circuit 140 selects any one of paths SW-A to SW-D. In this example, since four paths are provided in the SW circuit 140, two signal output lines (2 bits) are used. A signal having a frequency significantly lower than that of a signal passing through the SW circuit 140 is used as the control signal outputted from the baseband circuit 110.
A level conversion circuit 120 inputs two control signals outputted from the baseband circuit 110, converts voltage levels of the respective signals into those which allow a logic circuit 130 to operate in an appropriate manner, and then outputs the signals thus obtained. The logic circuit 130 further converts the converted signals outputted from the level conversion circuit 120 into four switching signals and outputs the four switching signals having been converted. For example, among combinations of a Low level “0” and a High level “1” of the two respective converted signals, the logic circuit 130 assigns “00”, “01”, “10” and “11” to a switching signal A, a switching signal B, a switching signal C and a switching signal D, respectively, and selects any one of the paths SW-A to SW-D included in the SW circuit 140 based on the switching signals A to D (i.e., turns the SW circuit 140 on).
FIG. 14 is a diagram illustrating an exemplary structure of the conventional level conversion circuit 120. The number of the level conversion circuit 120 to be provided is determined in accordance with the number of control signals outputted from the baseband circuit 110. Thus, in the aforementioned example, two level conversion circuits 120 are provided. FIG. 15 is a diagram illustrating an input-output characteristic of the conventional level conversion circuit 120 shown in FIG. 14.
Between an input terminal 151 which inputs a control signal outputted from the baseband circuit 110 and the ground, a bleeder resistance (R1) 121, a level shift circuit 122 and a bleeder resistance (R2) 123, all of which are connected in series with each other, are inserted. An output terminal 152 is connected to an output side k of the level shift circuit 122. A relationship between an input voltage Vi of the input terminal 151 and an output voltage V0 of the output terminal 152, i.e., an inclination of the characteristic shown in FIG. 15 is determined based on a resistance division ratio of the bleeder resistance 121 to the bleeder resistance 123. Specifically, Vo=Vi×R2/(R1+R2) is satisfied in region B.
The level shift circuit 122 defines the input voltage Vi obtained when the output voltage Vo starts to appear at the output terminal 152, i.e., an inclination start position Vi(L) of the characteristic shown in FIG. 15, in region A, Vo is 0V. The level shift circuit 122 is used for increasing a switching margin in the case where the input voltage Vi is a logic value “Low”. When a diode is used, for example, as the level shift circuit 122, a value ranging approximately from 0.5V to 0.6V will be obtained.
FIG. 16 is a diagram illustrating a simulation result obtained when using the conventional level conversion circuit 120 shown in FIG. 14. During a simulation, the bleeder resistance 121 and the bleeder resistance 123 are set at 300 kΩ and 600 kΩ, respectively, and a GaAs-MESFET having a Schottky gate is used as a diode of the level shift circuit 122.
(a) of FIG. 16 shows a characteristic of the input voltage Vi versus the output voltage Vo of the conventional level conversion circuit 120. The GaAs-MESFET having the Schottky gate (Φb to about 0.4V) is used as a diode, and thus the output voltage V0 rises up (appears) from approximately 0.4V.
For example, it is assumed that the logic circuit 130 using an enhancement type GaAs-MESFET is provided subsequent to the level conversion circuit 120, and a threshold value Vth of the logic circuit 130 is +0.2V. In this case, a voltage level is set as an input Low level because the output voltage Vo is 0V when the input voltage Vi is within a range from 0 to about 0.4V(=Vi(L)), while the voltage level is set as an input High level because the output voltage Vo is 0.66V or more when the input voltage Vi is 1.5V(=Vi(H)) or more. Thus, it is possible to realize a level conversion circuit capable of outputting a voltage less than or equal to the threshold value Vth when the voltage level is the input Low level, and also capable of outputting a voltage greater than the threshold value Vth when the voltage level is the input High level.
(b) of FIG. 16 shows a characteristic of the input voltage Vi versus an inflow current Ii (a current flowing from the input terminal 151) of the conventional level conversion circuit 120. The inflow current Ii starts to flow at the same time when the input voltage Vi rises up. As is clear from (b) of FIG. 16, when the input voltage Vi is 1.5V, a current of 1.1 μA flows from the input terminal 151, while when the input voltage Vi is 5.0V, a current of 4.9 μA flows from the input terminal 151.
The simulation result of the conventional level conversion circuit 120 is shown in a table 1 below.
TABLE 1Vo whereVi = 1.5 VIi where Vi = 1.5 VIi where Vi = 5.0 V0.66 V1.1 μA4.9 μA
Moreover, these days, the miniaturization of LSIs which are mounted on a portable terminal has advanced, and the power consumption of digital circuits such as the baseband circuit 110 has been reduced accordingly. Under such circumstances, an allowable current value of an output terminal included in the baseband circuit 110 also tends to decease. Therefore, in order to decrease the inflow current Ii flowing to the level conversion circuit 120, the prior arts using the bleeder resistances 121 and 123 mentioned above are under pressure to increase values of the bleeder resistances 121 and 123. For reducing a current value to one-tenth thereof, it is necessary to increase the value of the bleeder resistance by ten times.
However, in the case where a sheet resistance of approximately 1 kΩ/□ is used in the semiconductor processing, it is inevitable, in a method of increasing this resistance value, that a chip area be increased in accordance with an increase in the resistance value even if a resistance value is only several hundreds of kΩ.